1. Field of the Invention
The invention relates to a correlator, and more particularly to a correlator suitable to a CDMA type receiver.
2. Description of the Related Art
As is known, in spread spectrum system, a signal is modulated by a transmitter, spectrum-spread through the use of pseudorandom noise code, and then, transmitted. A receiver inverse-spreads a received signal through the use of pseudorandom noise code which is identical with the pseudorandom noise code (PN) having been used by a transmitter for spread, in order to demodulate the received spectrum-spread signal.
In these days, CDMA (Code Division Multiple Access) communication system in which spread-spectrum type pseudorandom noise code is assigned to each communication is expected as a standard radio-communication system for a mobile terminal in a mobile communication system.
In the CDMA communication system, for instance, user data spread with pseudorandom noise code inherent to each of users are synthesized in the same frequency band, and then, is transmitted, and a receiver extracts desired data through the use of pseudorandom noise code of a user who the receiver wants to make communication.
The CDMA communication system has advantages that it presents a high efficiency at which spectrum is used, it has a high resistance to multi-pass, communication can be kept highly in secret, and so on.
In the CDMA communication system, it is necessary for a receiver unit to make synchronization in timing with pseudorandom noise code included in a signal. That is, both timing at which pseudorandom noise code series occur in a received signal and timing at which pseudorandom noise code series prepared by a receiver occur are estimated with accuracy of one chip or smaller, and a pseudorandom noise code series generator is made to start its operation at the estimated timing, that is, synchronization capture is carried out.
In a direct spread (DS) system, a received signal is missed, if a synchronization position is deviated even slightly. Hence, it is necessary for a receiver to carry out synchronous trace in which a received signal having been successfully captured is monitored in order to prevent pseudorandom noise code series from deviating with respect to time.
To this end, a transmitter inserts a fixed pattern (which is a pattern for making synchronization, and is also called “pilot symbol”) determined in advance as a synchronization signal, into a signal, and then, transmits the signal. A receiver calculates correlation between a received signal and a fixed pattern for detecting synchronization. Thus, detection of a received signal and timing synchronization control are accomplished.
A direct spread (DS) type spectrum spread communication device is disclosed in Japanese Patent No. 2850959 (B2), for instance.
The conventional direct spread type spread communication device disclosed in the Japanese Patent operates as follows.
A spread spectrum signal having been received through an antenna is converted into a base-band signal in a local oscillator and a low-pass filter both constituting a signal converter. The base-band signal is sampled in a sampling and holding circuit, for instance, by every ½ chip. The thus sampled signal is transmitted to a correlator comprised of a matched filter. The correlator multiplies one symbol of pseudorandom noise code in the received signal by one symbol of pseudorandom noise code prepared in advance in each of chips, calculates a total sum of the products, and transmits the sum to a synchronization detector.
FIG. 8 illustrates an example of a correlator which detects correlation between a sampling signal and pseudorandom noise code. The correlator is comprised of a shift register 301, a coefficient generator 302, multipliers 3031 to 3034, and an adder 304.
As illustrated in FIG. 8, a spread spectrum signal (input signal) 300 having been converted into a base-band signal is successively stored into the shift register 301 chip by chip.
The coefficient generator 302 generates pseudorandom noise code series. The spread spectrum signal stored in the shift register 301 and the pseudorandom noise code series are multiplied by each other chip by chip in each of the multipliers 3031 to 3034. The products are transmitted to the adder 304 from the multipliers 3031 to 3034, and the adder 304 calculates a total sum of the products. The sum is transmitted as an output signal 305 from the adder 304.
When the pseudorandom noise code series and the received spread spectrum signal are coincident in timing with each other, the output signal 305 transmitted from the adder 304 is in maximum, or makes a matched pulse. The matched pulse is detected by a matched pulse detecting circuit (peak detecting circuit, not illustrated) and a synchronization detector (not illustrated), and inverse-spread demodulation is carried out based on the thus obtained synchronization data.
The above-mentioned Japanese Patent No. 2850959 also discloses a modulator for capturing synchronization in spread spectrum communication, including a synchronization circuit. The synchronization circuit includes a symbol integrator. The symbol integrator inverse-modulates a correlation value, based on either a theoretical value of a symbol, corresponding to a correlation value transmitted from a correlator, or demodulated judgment of an unknown symbol, adds a plurality of symbols to one another to calculate added power of the symbols, to thereby calculate power.
In the CDMA communication system, a signal having been modulated in spread spectrum would have a broad band, and hence, would have a quite low power spectrum density. Accordingly, a signal-to-noise (S/N) ratio is quite small at a front end of a receiver. In other words, since an input signal would have a quite small S/N ratio in equivalence of a chip rate, it would be necessary for a receiver to have a fixed pattern as a pattern for establishing synchronization, which fixed pattern is significantly long with respect to a chip, in order to establish accurate timing synchronization. Hence, a receiver has to include a large correlator as a circuit for capturing synchronization.
For instance, if the correlator illustrated in FIG. 8 were designed to be longer, the shift register 301 and the adder 304 would be increased in size, and the number of multipliers 3031 to 3034 would be increased. As a result, the correlator would consume much power, resulting in increasing difficulty in saving power consumption and fabrication in lower cost in a mobile terminal device such as a CDMA cellular phone.
For instance, if a correlator is designed to receive a fixed pattern having a code length N, comprised of signals obtained by spreading a fixed symbol having a K symbol length at a spreading ratio of M chip/symbol, the correlator would be constructed to have a length of M×K chip.
In addition, if the correlator illustrated in FIG. 8 were designed to be longer, the shift register 301 would have to be constructed longer, resulting in that calculation of a correlation value would take longer time, and hence, it would take longer time until synchronization capture is accomplished.
FIG. 7 illustrates another conventional correlator. The correlator illustrated in FIG. 7 is comprised of a multiplier 201 which receives an input signal 200 and a spread coefficient Ci, and multiplies them by each other, an adding circuit 202, and a latch circuit 203.
The multiplier 201 multiplies the received input signal 200 and the spread coefficient Ci by each other, and transmits the resultant product to the adding circuit 202 through its one input terminal. The adding circuit 202 receives the previous accumulated value (an initial value thereof is equal to zero) through other input terminal thereof, and adds the product and the previous accumulated value to each other. The resultant sum is latched in the latch circuit 203, and is fed back to the adding circuit 202 through the other input terminal. The adding circuit 202 adds the fed-back sum and next sum to each other.
The conventional correlator illustrated in FIG. 7 could have the smaller number of multipliers than that of the parallel type correlator illustrated in FIG. 8. That is, though the correlator illustrated in FIG. 7 could have only one multiplier, the correlator would take longer time to calculate a correlation value than that of the correlator illustrated in FIG. 8.
Specifically, for instance, if correlation having a length N is detected by means of the conventional correlator illustrated in FIG. 7, multiplication is carried out N times and addition of the resultant products is carried out once in order to output a correlation value. Accordingly, a time necessary for obtaining a correlation value increases in proportion to the length N, and hence, it would take much time to accomplish synchronization capture.
In order to accomplish smaller power consumption and lower costs in a mobile terminal device such as a cellular phone, it would be necessary to simplify a circuit structure of the correlator to thereby reduce hardware in size. In addition, it would be also necessary to operate the correlator at a higher rate.
However, the conventional correlators illustrated in FIGS. 7 and 8 cannot meet such requirements as mentioned above.
In view of the above-mentioned problems, it is an object of the present invention to provide a correlator to be used in a receiver in CDMA communication system which correlator is capable of significantly reducing a circuit size.
It is also an object of the present invention to provide a correlator which can prevent an increase in a circuit size, and is adaptive to a plurality of fixed patterns used for establishing synchronization.